Torsten Maehne

@MarcinOrlowski: > What about availability of Java 21 runtime in major distros? IMHO, we shouldn't be too concerned about that, as the JRE gets bundled with the application when building...

> How'd you manage to use RAM? I thought it wasn't FPGA-supported Please tell me how did you manage to do that @SLicudis: See [my answer](https://github.com/logisim-evolution/logisim-evolution/discussions/2007#discussioncomment-9498353) to your question #2007.

You can already highlight a net by clicking with the hand tool on a wire while value propagation is active. This will also add a callout showing the nets' value....

Your enhancement request is related to issue #1959. Signal widths are currently limited to 64 bits. Currently, your only option is to split up the 192-bit words on three 64-bit...

Just enabling VHDL simulation is not sufficient. You need to install a supported VHDL simulator (currently only Mentor/Siemens' ModelSim or Questa Sim) and provide the path to the `bin/` directory...

> Edit: would intel questa be alright? The other "Siemens" is like business type. Mentor Graphics was the original company behind ModelSim/Questa Sim, which was bought by Siemens several years...

That is not that easy, as it requires changes in many places. See, e.g., [the PRs which were required for lifting the limitation from 32 bits to 64 bits](https://github.com/logisim-evolution/logisim-evolution/pulls?q=is%3Apr+64+bit+is%3Aclosed). PRs...

@gtxzsxxk: Could you please try with the [latest nightly builds](https://github.com/logisim-evolution/logisim-evolution/actions/runs/8993940035) compiled with JDK 21?

This may be a duplicate of issue #1452.

@gtxzsxxk: Thanks for testing! So this issue seems to be resolved. I am closing this issue. Feel free to reopen in case of a regression (or check whether issue #1452...