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Migen Namer __main__ Decoration

4

This isn't necessarily a bug, but I do feel it makes Verilog identifiers that Migen generates more difficult to read. Migen has a tendency to decorate Verilog identifiers with the...

cr1901

Migen outputs incorrect verilog in specific use-case

6

I wrote a Migen code which used MultiReg for signal synchronization across clock domains and the relevant section is similar to the test code below: ```python from migen import *...

rohitk-singh

review expression size and signedness

1

* verilog-2001, 4.4.2: self-determined expressions size: `answer = (a + b) >> 1; //will not work properly` and `answer = (a + b + 0) >> 1; //will work correctly`...

jordens

Empty FSM states do not produce expected behavior

1

E.g. this should produce an FSM that goes to the B state and stays there: ``` self.submodules.fsm = FSM(reset_state="A") self.fsm.act("A", NextState("B")) self.fsm.act("B") ``` but it does something else.

whitequark

chained comparisons are not implemented correctly

1

These should be identical, and indeed they are in Python: ```python class OK(Module): def __init__(self): self.a = Signal(8) self.b = Signal(8) self.c = Signal() self.comb += \ self.c.eq((self.a == 0)...

whitequark

Should Migen generate explicit Verilog for mismatched bit vector lengths (rather then relying on implicit Verilog behaviour?)

23

@bunnie has been working with LiteX / Migen recently and mentioned he thought following issue would be a big source of bugs in LiteX / Migen designs. I would like...

mithro

AsyncFIFO reset

2

(From #72) Currently a reset from either the read or from the write CD resets that side's (and only that side's) address (Gray) counter. This is probably wrong as it...

jordens

FullMemoryWE and SplitMemory break direct access to memory in simulation

1

Since `FullMemoryWE` and `SplitMemory` replace/remove the old memories, they can't be accessed directly in simulation. Both decorators should provide transparent access to the (new) underlying memories.

jordens

Records with 0 fields generate invalid verilog

4

When defining a record with no fields, as in `_layout = []` and then using `raw_bits()`, it will generate invalid verilog, e.g.: `assign {} = x;`

nakengelhardt

Cat(..)[slice] on LHS needs a proxy

4

When attempting to use Record.raw_bits() to create a bus to manipulate in further Migen expressions, Migen will generate the concatenation "in place" in the generated Verilog code for each use...

cr1901