review expression size and signedness

[jordens]

• verilog-2001, 4.4.2: self-determined expressions size: answer = (a + b) >> 1; //will not work properly and answer = (a + b + 0) >> 1; //will work correctly and table 29, Signal(4).eq((Signal(4, reset=0xf) + Signal(4, reset=0xf)) >> 1)
• Mux() is probably unsigned if the first operand (the conditional, usually a comparison) is unsigned: Mux(1, Signal((3, True), reset=-1), Signal((2, True), reset=-1))
• Cat([Signal((17, True)) for i in range(4)]).eq(Cat([Signal((17, True)) for i in range(4)])) drama and simulation/implementation mismatch (or vivado bug) of https://github.com/m-labs/artiq/commit/0b086225a9ede6bd6a9fe8b8efe0056251554336

[whitequark]

Triage: fixed in nMigen, which relies on Yosys to emit Verilog. The Yosys verilog backend is heavily tested using vloghammer.