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Python logical operator 'and' silently dropped

18

The following migen snippet: ``` If((self.addr == 0x18a) and (self.joy_enabled == 1), ``` produces the following Verilog: ``` if ((addr_1 == 9'd394)) begin ```

tdaede

[migen][sim] How to import verilog source into migen design file ?

1

Hello, I'm trying to import verilog code into migen design as below: First I created shifter.v: ```verilog module shifter( input sck_i, input sdi_i, output sdo_o, input csn_i, ); reg [7:0]...

henrydang80

constrain CDCs with max_delay [vivado]

1

Apparently, the proper way to constrain some CDCs (Both AsyncResetSynchronizer and transfer via GreyCounters) should use a max_delay constraint and not a false path. https://forums.xilinx.com/t5/Vivado-TCL-Community/How-to-set-timing-constraint-in-this-case/m-p/510771/highlight/true#M2049 How would one implement this?...

jordens

The following code, with x a n-bit signal: `Cat(x+1, 1)` should produce a n+2 bit value (carry from the addition, plus 1 added by Cat). The simulator implements this behavior,...

sbourdeauducq

I have seen mismatching behavior between migen simulation and Vivado synthesized designes involving `Mux()` (the ternary/conditional operator) and signed `Signal()`. Verilog-2001: "If the lengths of expression2 and expression3 are different,...

jordens

<< seems buggy

2

E.g.: ``` s = Signal(max=8) self.comb += s.eq(1) (s

whitequark

support asymmetric dual-port memories

1

Dual-port block RAMs in some FPGAs can have ports with different sizes. This feature cannot currently be used with Migen.

sbourdeauducq

.part() is converted to Verilog that can evaluate to 'x

1

`.part()` as implemented corresponds to the semantics of Yosys `$shiftx` cell. It should use the `$shift` cell. See https://github.com/YosysHQ/yosys/pull/744 for an example of how to emit Verilog for that cell.

whitequark

Finalization is order-dependent, leading to footguns

1

See https://github.com/m-labs/microscope/pull/1.

whitequark

Negative initialization produces incorrect verilog

8

Migen: self.idx = Signal(max=depth, reset=-1) Generated Verilog: reg [3:0] sdram_bankmachine0_cmd_buffer_lookahead_idx = 4'd-1; The assigned value should be -4'd1 instead to be valid Verilog. Not my favourite thing about the language.

JohnSully