incorrect Cat element width in Verilog export

[sbourdeauducq]

The following code, with x a n-bit signal: Cat(x+1, 1) should produce a n+2 bit value (carry from the addition, plus 1 added by Cat).

The simulator implements this behavior, but the Verilog output is {1'b1, x+1}, which is only n+1 bits (the carry bit from the addition is lost).