sim/verilog mismatch: mux

[jordens]

I have seen mismatching behavior between migen simulation and Vivado synthesized designes involving Mux() (the ternary/conditional operator) and signed Signal().

Verilog-2001: "If the lengths of expression2 and expression3 are different, the shorter operand shall be lengthened to match the longer and zero-filled from the left (the high-order end)."

I assume (but I'm not entirely sure) that means that the Mux() is supposed to be always unsigned.

Currently, migen-sim just takes expression2 or expression3 and carries over their signedness.