luck-codeer

generate_tech_xml_files.sh

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#### Description Completing the conversion from units to exponential scale. #### Related Issue When running generate_cmos_tech_data.pl with hspice 2017, you may come across an issue where the current values need...

Regarding the issue of running generate_cmos_tech_data.pl with hspice 2017

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Hi，developers I conducted two measurements of the same FPGA architecture at low temperatures with power supply voltages of 0.7V and 0.8V, the value of vth0 was also changed to 0.3...

About the meaning of lut_input, the composition of a tile and how to measure the power consumption of a tile.

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Hi, I have two questions to ask you, First, in coffe/fpga.py, line 6409, I want to know why the delay of LUT equals the delay of lut_input plus the maximum...

About [R, C] in the metal layer

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I would also like to ask you a question about how to obtain the resistance and capacitance values per unit length in this metal layer. If I want to obtain...

About the issue of abnormal power consumption evaluation at low temperatures

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Hello, Professor Betz. I apologize for bothering you again. I have encountered some phenomena in my work on designing FPGA architectures at low temperatures using COFFE and VTR. After consulting...

Hello, Professor Betz. Thank you for your reply last time, I have already understood the meaning of the critical path delay in COFFE. Now I have encountered a problem, which...

About the meaning of crit_path_delay

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Hello, Professor Betz. Thank you for your previous reply. This time, I would like to ask if the critical path delay in COFFE is different from that in VTR, and...

About the minimum supported temperature of COFFE2

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Hi, I am using your tool COFFE2 to do experiments on the performance (delay and power consumption) of FPGA components at low temperature. The results obtained are shown in the...