luck-codeer

It is worth noting that when I set vth0 to 0.2, the power consumption increases as VDD increases, although the dynamic power consumption ratio is still not close to 1,...

Hi, Professor Betz. I understand the reason now. There was a problem with the leakage current of a line in the 22nm.xml file generated by generate_cmos_tech_data.pl, and I have fixed...

Ok, Professor Betz. This is the issue I encountered when using generate_cmos_tech_data.pl to generate 22nm.xml using hspice 2017. I'm not sure if this problem also occurs in other versions of...

hello, professor Betz. I have already submitted the relevant pull request, but I still have some questions on this issue(https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/2424). Could you provide me with some advice?

May I ask if you have resolved this issue? I have also encountered a similar problem.

When encountering such an issue, one might consider using the command "../scripts/run_vtr_task.py power/power_nofrac_22nm" as an alternative solution.

Well, what I meant is to conduct the experiment using .xml in run_task.py, not with stratix10_arch.xml. Also, I believe it will use the corresponding synthesis tool. Here are some of...

When running generate_cmos_tech_data.pl with hspice 2017, you may come across an issue where the current values need to be converted into exponential notation with the "e" notation. Additionally, certain lines...

Sure. Professor Betz, I have submitted a PR regarding this issue. you could take a look and see if it's helpful.

Professor Betz，I still have some questions that I don't quite understand. I would appreciate it if you could provide me with some guidance when you have some free time. When...