circt
circt copied to clipboard
llvm
Circuit IR Compilers and Tools
## Proposed changes Add a new Dialect, `CHALK`, to `circt` that models VLSI circuit layout data(e.g. Magic VLSI, GDSII, OASIS). ## Types of changes - [x] New circt Dialect -...
This PR implements initial support for the left streaming operator `{
The `NonLocalAnchor` can be used to specify the instance path for uniquely identifying any operation globally. It is used to attach nonlocal annotations in the `FIRRTL` dialect. Currently it is...
See issue #3002 Build reduction ops when possible to reduce operations of the form `or(a[0], a[1], ..., a[n])` to `icmp ne(a, 0)`. This optimization is implemented for the `and`, `or`...
As of now, we don't have a good way to compute the resulting type of a parameter expression or compare the resulting types _without_ providing the specific parameter values from...
The following IR is derived from a test case of https://github.com/llvm/circt/pull/3116 which workarounded verilator hangs. ```mlir hw.module @Verilator3405() -> () { %state = sv.reg : !hw.inout sv.initial { %state_read =...
combinatorial cycles are allowed in HW, but prettify verilog is non-deterministically (I think) failing on them. It is also sometimes expanding the xor below to a chain of 3 xors....
getLineAndColumn expects an optional bufferID. getMainFileID always returns 1, so in cases where the bufferID is not 1, this can cause a crash. Remove the unnecessary call to getMainFileID and...
Input: ```mlir firrtl.circuit "Foo" { firrtl.module @Foo() { %invalid_ui0 = firrtl.invalidvalue : !firrtl.uint } } ``` Output of `circt-opt -lower-firrtl-to-hw` contains `firrtl.invalidvalue` for some reason. ``` hw.module @Foo() { %invalid_ui0...
This PR adds a new `FIRRTL` op for specifying a cross module reference, also known as an XMR. The XMR represents a non-local hierarchical name to a net. The hierarchical...