PrettifyVerilog breaks with combinatorial cycles

[darthscsi]

combinatorial cycles are allowed in HW, but prettify verilog is non-deterministically (I think) failing on them. It is also sometimes expanding the xor below to a chain of 3 xors.

module {

hw.module @Foo() -> (b: i1) {
  %true = hw.constant true
  %0 = comb.xor %0, %true : i1
  hw.output %0 : i1
}

}