[CHALK] Initial commit of new circt dialect, CHALK, for 2D VLSI Layout Data

[pbonh]

Proposed changes

Add a new Dialect, CHALK, to circt that models VLSI circuit layout data(e.g. Magic VLSI, GDSII, OASIS).

Types of changes

• [x] New circt Dialect
• [x] New circt Passes

Checklist

• [x] Example FileCheck Tests for new Dialect/Passes
• [ ] Documentation of CHALK operations
• [ ] Documentation of passes

Further comments

I'd like to introduce a new dialect that I've named, CHALK, with the intent of modeling 2D VLSI layout data.

The MLIR developer guide encourages contributors to upstream dialects in small incremental patches, so I have kept this PR as small as possible. It currently only models 2D rectangles with an initial placement pass that removes the overlap, but I intend to add other types in the near future(Trapezoids, Paths, Shape References, etc.).

CHALK is modeled after existing layout tools/formats(e.g. Magic VLSI, GDSII, OASIS), with the intent that circt will eventually be able to lower directly to these types for better interoperability.

My long term vision is that circt will be able to implement logic & physical synthesis algorithms as IR Passes/Transformations. If accepted, my next steps will be to implement the incremental placement algorithm developed by Chatterjee & Brayton:

S. Chatterjee and R. Brayton, "A new incremental placement algorithm and its application to congestion-aware divisor extraction,"
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004., 2004, pp. 541-548, doi: 10.1109/ICCAD.2004.1382637.

which performs boolean divisor extraction based on 1) optimal placement due to wire-length and 2) reduction in literal(boolean term) count. This could be accomplished by embedding CHALK shapes in either the HW or FIRRTL op regions, computing the wire-length gains, and rewriting the logic according to the cost calculated from the represented shapes.

[mikeurbach]

My long term vision is that circt will be able to implement logic & physical synthesis algorithms as IR Passes/Transformations.

I think this is a great long term goal that many of us would be happy to see. Would you be interested in discussing CHALK at a future CIRCT open design meeting (https://docs.google.com/document/d/1fOSRdyZR2w75D87yU2Ma9h2-_lEPL4NxvhJGJd-s5pk/edit#)?

In the meantime, I'll take a look at the initial commit.

[pbonh]

Thanks for the feedback @mikeurbach!

I've made the requested updates but I noticed that a few of the automated checks failed. One of them complained about inheriting from TypeDef in my Types tablegen file, but I don't run into this error on my end. Any ideas?

[mikeurbach]

Hmm I don't know offhand what's off, but perhaps upstream CIRCT has updated the LLVM version and you need to update your local copy?

Regarding the VariadicRegion, if you intended for the region to be optional, I think SizedRegion<1> is going to enforce there is exactly one region.

[pbonh]

Thanks, that was indeed the issue!

I've fixed it and ran clang-format manually, so hopefully that cleans up all of the issues.

[teqdruid]

I too am interested in the long-term vision for this dialect. The term "cell" implies to me that it would be used to create standard cell libraries...? Or would it be used in fully custom designs? Which dialects do you imagine it being lowered from?

It would help to have a rationale document in this (or another) PR describing where you think it fits in, especially in terms of interactions with other dialects. I know very little about VLSI design other than it's wildly complex.

[pbonh]

Hi @teqdruid, I agree that a rationale document would help answer a lot of these questions, I'll start converting my notes and open another PR.

[pbonh]

Still not sure why I'm not seeing some of the linking issues in the Github workflow, but they should be fixed with this latest checkin. Thanks for your patience @mikeurbach

[darthscsi]

@pbonh Do you know of the Circt Open Design Meeting? It's on Wednessdays at 11 Pacific. It would be great if you could take a week to talk about this work. https://docs.google.com/document/d/1fOSRdyZR2w75D87yU2Ma9h2-_lEPL4NxvhJGJd-s5pk/edit?usp=sharing

[pbonh]

Hi @darthscsi. Yes, I've signed up to give a future presentation on CHALK, though I'm not prepared for tomorrow, so please stay tuned!

@mikeurbach, I fixed my branch rebase, so there shouldn't be any conflicts, could you re-run the workflow?

[darthscsi]

Hi @darthscsi. Yes, I've signed up to give a future presentation on CHALK, though I'm not prepared for tomorrow, so please stay tuned!

When you are ready, feel free to pick an open day.

[darthscsi]

Haven't heard anything for a while, converting to draft.