circt
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llvm
Circuit IR Compilers and Tools
Currently a data type of a memory is flattened to an integer. However combined with unused field removal https://github.com/llvm/circt/blob/11ad8a882fbcacb75c40fbf9c946eb35e2e43c89/lib/Dialect/FIRRTL/FIRRTLFolds.cpp#L2812, sometimes it makes difficult to verify LEC between two versions. Example:...
I discovered that compreg didn’t have a custom printer, so it was using the default format. That format wasn’t handling quoting correctly. The solution was to add a small custom...
Hello, I'm having an issue when trying to import Verilog generated with Yosys. It leads into a combinatorial cycle that isn't present in the Verilog program. Here is a simple...
Hi there, I have found a bug in the code generation with the Calyx backend in the latest version of CIRCT. In the generated Verilog the reset signal are not...
Remove the extract test code feature from firtool, which has been deprecated in favour of using bound layers.
Hi, all! Let's consider a such `Verilog` example: ```verilog module top (input clk, input rstn); reg r1; always @(posedge clk or negedge rstn) begin r1 = 0; end endmodule ```...
This commit fixes two different corner cases in aggregate generation when running with firrtl generated by chipyard 1. a clock signal could reside in an "aggregate". This is caused by...
This issue can be reproduced by the attached mlirbc and circt-reduce built at 40962a320. An easy fix can be introduced to guard the isBeforeInBlock, but I think it exposes a...
Possible fix for #8810 - Add Clocktype to ClockedAsser Replacing I1 for clk - Add MLIR test changes in test/Dialect
When generating a single verilog file, the layer files are included, even if they are not generated, leading to errors. 1. untar [no-include.tar.gz](https://github.com/user-attachments/files/22542462/no-include.tar.gz) 2. Run `firtool '--format=mlir' --disable-all-randomization -strip-debug-info '-disable-layers=Verification'...
