[BUG] Wrong propagation of reset signal and clock

[gabrielrodcanal]

Hi there, I have found a bug in the code generation with the Calyx backend in the latest version of CIRCT. In the generated Verilog the reset signal are not used directly but they are renamed with a couple of wires:

  wire        ret_arg0_reg_clk = 1'bz;	// adder.mlir:1:1
  wire        ret_arg0_reg_reset = 1'bz;

However, the assignment is not correct and this causes the control FSM to hang. The bug is fixed by fixing the assignment:

  wire        ret_arg0_reg_clk = clk;	// adder.mlir:1:1
  wire        ret_arg0_reg_reset = reset;

To reproduce the issue use the following adder.mlir:

func.func @adder(%a: i32, %b: i32) -> i32 {
  %sum = arith.addi %a, %b : i32
  return %sum : i32
}

And the command hlstool --calyx-hw adder.mlir --split-verilog -o=out. The issue is in out/adder.sv. I can also provide a Verilator testbench if needed.

Edit: I have managed to isolate the faulty pass. The problem happens at the canonicalization step at https://github.com/llvm/circt/blob/407c3d2de3a1f2814d317108e979115ddc9529f5/tools/hlstool/hlstool.cpp#L454

You can see this that here the clock and reset signals are passed to the FSM from the top module.

hlstool --calyx-hw adder.mlir --output-level=post-compile --ir

Whilst here two Z-constants are created:

hlstool --calyx-hw adder.mlir --output-level=rtl --ir

You can isolate the problematic pass with:

hlstool --calyx-hw adder.mlir --output-level=post-compile --ir | circt-opt --lower-calyx-to-hw --canonicalize

(Simply remove --canonicalize to see how the clock and reset signals are still used before that).