circt
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Circuit IR Compilers and Tools
Consider the following circuit: ``` firrtl FIRRTL version 5.2.0 circuit Foo: layer A, bind: public module Foo enablelayer A: ``` If this is compiled with the option to disable `layer...
Problem file (reduced with `circt-reduce`: ```mlir module { %false = hw.constant false fsm.machine @mbx_fsm(%arg0: !seq.clock, %arg1: i1, %arg2: i1, %arg3: i1, %arg4: i1, %arg5: i1, %arg6: i1, %arg7: i1, %arg8:...
I have noticed that enabling [the SROA pass](https://github.com/llvm/circt/blob/d1c996adc6b958b20ce25e98d95de90de2ae8613/tools/circt-verilog/circt-verilog.cpp#L338) in circt-verilog causes logical equivalence checkers to report mismatches when round-tripping Verilog through CIRCT. I'll comment that pass out again since it...
Currently AIG dialect is used as core representation for circt-synth flow but for synthesis there are few other operations I'd like to introduce but not limited to AIG. From that...
Input: ```firrtl FIRRTL version 5.1.0 circuit SignedPrintETC : public module SignedPrintETC : input clk : Clock input test : SInt printf(clk, UInt(0h1), "%0d", test) ``` When using `--extract-test-code` this produces...
Add a check for the case described in #8610
The FIRRTL here is invalid, produced while manually reducing a larger test case. Looks like we fail hard if there aren't enough operands to (f)printf? Input: ```firrtl FIRRTL version 5.1.0...
```firrtl FIRRTL version 4.1.0 circuit Foo: public module Foo: input sel1 : UInt input a : UInt[1] input b : UInt output o : UInt connect o, mux(sel1, a, b)...
Consider the following file in the MLIR FSM dialect: ```mlir module { fsm.machine @mbx_fsm( // Inputs from Verilog module %mbx_range_valid_i: i1, %hostif_abort_ack_i: i1, %mbx_error_set_i: i1, %sysif_control_abort_set_i: i1, %sys_read_all_i: i1, %writer_close_mbx_i:...