lizajoseph

Thanks Alex, I ran the tests in cocotbext-eth->eth_mac, gmii, gmii_phy, mii, mii_phy, ptp_clock, ptp_clock_sim_time, rgmii, rgmii_phy, xgmii. How is the DUT connected to these tests? I see that each of...

I invoked the behavioral simulation after loading the fpga.xpr, However the simulation in the waveform does not generate any clock, the mmcm_locked remains "0" and the qsfp_tx_n[3:0], qsfp_tx_p[3:0], qsfp_rx_n[3:0], qsfp_rx_p[3:0]...

> The Alveo example design testbench is here: https://github.com/alexforencich/verilog-ethernet/tree/master/example/Alveo/fpga_25g/tb/fpga_core Hi Alex, When I try to run simulation using "make WAVES=1", I get the following error. Am I missing anything in...

The issue was with "scapy" that needs to be installed as most testcases uses scapy libraries. After installing scapy I was able to run the testcases

I am trying to generate the bitstream but I am hitting the same error, was anyone able to proceed further? # create_ip -name mac_ip_encode -vendor xilinx.labs -library hls -module_name mac_ip_encode_ip...

> In your case, try change the vendor name to ethz.systems.fpga. I tried to change the vendor name from ethz.systems to ethz.systems.fpga, but getting the same issue

> I think you should try this repo, "https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP" It uses the same repo "[fpga-network-stack](https://github.com/fpgasystems/fpga-network-stack)" and I was able to generate the bitstream using that repo Thank you for your...

> I implemented it on U250. I don't know if it works on U50. > > Thanks, Hiruna Where you able to test the bitfile on U250 hardware?

> I use XRT interface to program the bitstream on U250. You should follow these two videos. > > * https://youtu.be/nvU2ZBnAaz4?si=Y2Mr1FXuQ4b4FYjQ > * https://www.xilinx.com/video/software/xilinx-xclbin-utility-introduction.html Okay, Thank you I did a...

> Don't just download the clone use this command `git clone --recurse-submodules https://github.com/fpgasystems/Vitis_with_100Gbps_TCP-IP.git` or `git clone --recurse-submodules [email protected]:fpgasystems/Vitis_with_100Gbps_TCP-IP.git` submodules needs to be downloaded. Yes, it works with your command. However...