vhd2vl

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Hi, currently the tests are failing due to three minor parenthesize inconsistencies. These are not real failures; the "golden outputs" against which the results are diffed ought to be updated....

amjoseph-nixpkgs

undefined type 'string'

1

Dear developer, I need to convert a VHDL file to verilog. I use ```./vhd2vl tb_fracn09.vhd tb_fracn09.v``` command for conversion. I got this error. `ERROR (line 17): undefined type 'string'.` What...

AMBiuki

I had what appeared to be a simple assignment of the form: wire

roboknight

This fixes the compatibility with the latest version of Verilog https://github.com/steveicarus/iverilog/releases/tag/v11_0

prusnak

When attempting to translate a VHDL entity whose PORT declaration contains a user defined type using the technique described here: https://stackoverflow.com/questions/16872950/can-custom-types-be-used-in-port-declaration, there is no way to inform vhd2vl of the...

shawnanastasio

VHDL-2008 initialization not handled

1

`signal douta_ram0 : std_logic_vector(31 downto 0) := 32D"0";` Lines like this return: > syntax error, unexpected NAME at "D" in line 82. Is there a way to handle the VHDL-2008...

trayres

Initial support for string type.

5

I think I found all the places this is used. I haven't been able to break it yet, at least.

jeinstei

Adds support for aliases.

2

Maps the VHDL alias keyword to the Verilog alias keyword.

martinhansdk

I tried to define a record type in a package file, saved as core_types.vhd: > package core_types is > type CPU_ToRAM is record > memAWriteEnable : std_logic; > memBWrite :...

hacksterous

yntax error, unexpected INTEGER at "integer" i

1

it could not read integer

chrhyd22