undefined type 'string'

[DarkC343]

Dear developer, I need to convert a VHDL file to verilog. I use ./vhd2vl tb_fracn09.vhd tb_fracn09.v command for conversion. I got this error. ERROR (line 17): undefined type 'string'. What should I do now? In advance, that VHDL file is tested and works.

[vedadux]

One thing I found effective is replacing it with integers or booleans, depending on the usage. In my case, it was just used in if statements for configuration of the circuit.