coreblocks

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Today I have synthesised coreblocks (with vector extension) in quartus and surprisingly I get 66 MHz Fmax for the slowest FPGA fabric (similar settings in nextpnr get Fmax ~45MHz). Analysing...

lekcyjna123

Use riscv-dv for randomized core testing

1

[RISCV-DV](https://github.com/chipsalliance/riscv-dv) is an instruction generator, which can be used for automatic testing of RISC-V cores. For execution, our existing Verilator+cocotb solution can probably be adapted. To verify execution, results should...

tilk

Run tests in loop

2

Currently each unit test is parameterized using two values important from running test case: seed and test_number. First set seed for random generator and second said us how many iteration...

lekcyjna123

Current implementation of loads/stores is a serious bottleneck of the CPU. It has only one RS slot, which means that if the core fetches two load/store instructions close to each...

tilk

Change get_result to send_result

1

This pull request, inspired by @Arusekk's deliberations, changes the movement of results from FU to announcement from pull-mode (announcement asks units for results) to push-mode (units announce the results themselves)....

tilk

Debug signals in `ModuleConnector`

1

Actually `auto_debug_signals` can not collect signals from `ModuleConnector` (probably because of using `args`/`kwargs`) so it has to be either investigated why `auto_debug_signals` can not get needed signals, or a `debug_signals`...

lekcyjna123

Analyse synthesis cost of FuDecoder

2

On the beginning of the project we did an assumption that decoding in FU will consist of two steps. First we decode `exec_fn` to internal one-hot representation and next we...

lekcyjna123

Fail on unsupported instructions

1

Decoder should set the illegal instruction signal when we don't support an instruction. Right now decoder happily decodes all instructions (doesn't matter if we have multiplication or division unit) and...

xThaid

Striped multiport fifo

2

Currently we have implemented a MultiportFifo, that gives very strong guarantees: - all elements are in time order - always maximum subset of methods is usable But this comes at...

lekcyjna123

Synthesis benchmark for submodules

2

It would be nice to have a benchmarks results for each part (submodule/connected component) which run in one cycle, so that we will know which modules are the biggest and...

lekcyjna123