coreblocks
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kuznia-rdzeni
RISC-V out-of-order core for education and research purposes
Recently we added new functionalities to transactron: - single caller methods - simultaneus transactions - ready_function We should extend "Advanced concepts" [section](https://kuznia-rdzeni.github.io/coreblocks/Transactions.html) with information about those features.
We need to implement floating point operations in order to support interesting applications. It probably isn't worth it to implement IEEE 754 in Amaranth, so the best course of action...
There is a very nice set of formal tests for the RISC-V architecture ([riscv-formal](https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md)). To use it, the processor should have a RVFI interface, which presents the currently retired instructions...
[Sprotty](https://github.com/eclipse-sprotty/sprotty) is a pretty cool diagramming framework, which could be used for dynamic exploring of the transaction graph. Unfortunately, the static graphs we can currently generate have lost some readability...
The current implementation of the instruction cache only services requests when not doing a refill. This introduces unneeded latency: for example, an instruction cache could return the first instruction as...
#473 added many venv and additional packages; see if they are actually needed.
Here is a PR to merge branch with implementation of vector extension. As for now I am going to merge here all already open PR's related with vector extension. List...
We don't have support in regression PySim for checking if core reported illegal instruction exception. I started by mistake a test with vector instructions on core without vector extension and...
To generate traces from cocotb benchmarks we need to pass `-t` flag, but additionally we have to manually clean the `test/regression/cocotb/build` directory, so that verilator files will be generated once...
It would be nice to integrate generation of verilog core with scripts to run benchmarks and regression, so that they can check if given configuration contains all extensions which are...
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RISC-V out-of-order core for education and research purposes