Yang Liu

RISC-V backend port

2

Hi there! I'm adding a RISC-V backend to chibicc and have made some progress. Just in case anyone is interested, I would like to mention this work here. The commit...

[Mach-O] Add -undefined dynamic_lookup option

1

Related #647

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I would like to add V support to riscv-config, this is the first PR.

Sample: [sample-elf-loading-error.zip](https://github.com/ptitSeb/box64/files/14472648/sample-elf-loading-error.zip) Error: ``` Looking for /path/to/sample-elf-loading-error Cannot create memory map (@0x10000d000 0x6000/0xfff) for elf "/path/to/sample-elf-loading-error" error=22/Invalid argument Error: Loading elf /path/to/sample-elf-loading-error ```

Download and run with `BOX64_DYNAREC=0`: https://github.com/love2d/love/releases/download/11.5/love-11.5-x86_64.AppImage. Note the segfault is not reproducible on RISC-V even with DynaRec off, which is rather strange.

Implements out-of-line clean calls on RISCV64, the implementation is similar to AArch64. Also enables out-of-line by default for all clean calls. With this patch, the previous trick of reducing `-max_bb_instrs`...

For now, we only support base+disp on RISC-V, there is no other way of addressing in the standard ISA extensions. This code path is executed by running `bin64/drrun gcc-13 hello.c`....