kidonglee
kidonglee
Dear Codasip, The synthesis condition is as follow, - dc ver = 2016.03 - scale factor = 0.563 // margin - clk = 400MHz // actual clock period = (1000/400)*0.563...
Dear Codasip, Did you check my comment above ? Actually, I wonder if the difference in speed between rocket and SweRV-EL2 is reasonable or not. If you have compared the...
> Hi @kidonglee, > We are meeting ~600Mhz for 16nm technology, **worst case corner**. > > Your scale factor seems very large! Based on that, your target frequency > 700Mhz....
I am sorry. I found that Cores-SweRVolf support SwerRV-EL2, also. I cloned el2 branch from git. And I modified fusesoc.conf file to add the folder containing swerf_el2.conf to library. Finally,...
> Please check https://github.com/chipsalliance/Cores-SweRV-Support-Package (SSP) . There is SweRVolf integrated already with SweRV EH1 1.8 and proven Open On-Chip Debugger 0.10.0+dev-01255-g2c909f8 (2020-09-29-10:12) . Your problem will high probably disappear if...
> My answer to your ssp install problem can be found in the issue you have opened there. > > Back to your question. The last 2 lines in $SWERVOLF_ROOT/data/swervolf_sim.cfg...
> My answer to your ssp install problem can be found in the issue you have opened there. > > Back to your question. The last 2 lines in $SWERVOLF_ROOT/data/swervolf_sim.cfg...
> Ah, I looked at your original report now and see that you already load an elf file. It looks like everything should be ok. I will need to check...
> This looks very strange. I will need to investigate Dear, olofk. Here is an additional wave image for the details on we[7:0] signals.  You can see that only...
> This looks very strange. I will need to investigate Dear olofk, I am sorry to bother you but I wonder if there is any progress with this issue. How...