hdlparse
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kevinpt
Simple parser for extracting VHDL documentation
Hi, I fixed some of your lexer regexes to properly parse parameters and not include comments in parsing. Below some before and after and Verilog code, based on which I...
Entities and architectures can end with "end some_name;" instead of "end entity;" or "end architecture;" The regex should check for any word (maybe with \w) instead of the specific keywords...
``` output logic [4:1] z, z2 ``` Parsing above gives: Ports: logic output 4 output 1 output z output z2 output
Just a small change to recognize "logic" keyword.
Hi Kevin, This is a good parser but it lacks a few things and since I am new to python I have struggled to make the necessary changes to fix...
In below case, the parser think "0", "Time", "1", and "Freq" are ports. I don't know which line make it confuse. To prevent that I added two "(r'/\*', 'block_comment', 'block_comment'),"...
I have a module which include a function in a module. In that cases, it thought 'value' and 'lshift' are ports. module xxx ( aaa ); output reg [1:0] aaa;...
This was the case I met. input wire [29:0] input_data; In that case, parser though that the port name is "_data".
lex.run(text) in parse_verilog(text) failed to correctly interpret portname that contain 'output' or 'input' as part of their name. I could resolve this by adding word boundaries (\b) to the regexp...
Hello Kevin, as GitHub hosts so many awesome lists (Python, Ruby, ...), I thought, we should create a list for VHDL too. I created [awesome-vhdl](https://github.com/VHDL/awesome-vhdl). Please create a pull request...
