Verilog and VHDL parser issues

[nvzach]

Hi Kevin,

This is a good parser but it lacks a few things and since I am new to python I have struggled to make the necessary changes to fix these problems. I have used your examples to parse verilog and VHDL and here's what I have observed:

1. Verilog 95 style ports not supported
2. How do I print the parameter value - the example doesn't do it.
3. Support for multidimensional ports - barfs after the initial array type declaration. For example a port declared below cannot be parsed effectively. output logic [31:0][2:0] xyz
4. If parameters are declared as arrays like the following they cannot be understood: parameter ADDR_RANGE = 32'h00002000, parameter integer DATA_WIDTH_ARRAY [5:0] = '{64, 64, 64, 64, 64, 64},
5. Cannot print generics value in VHDL example provided.

Would it be difficult adding/fixing these features.

Thanks

NZ