Ronan Keryell

Results 101 issues of Ronan Keryell

The section dives directly in a lot of gory details. I wonder whether it would not be more palatable to just talk about the default device selectors and from there...

There is still a lot of deprecated SYCL 1.2.1 device selector usage. This is a follow-up from https://github.com/codeplaysoftware/syclacademy/pull/72#discussion_r723980895 This is a generalization of https://github.com/codeplaysoftware/syclacademy/issues/54

There is no hardware description of memory hierarchy and hardware architecture in this part, so it is difficult to understand the problem we are solving here.

In `Lesson_Materials/Lecture_7_Introduction_to_USM/index.html` on slide "USM variants" it is unclear where these categories come from and how it relates to the ones we have in SYCL 2020. Is it some left-over...

Mainly using a part for Vitis IP which is installed by default.

Check for old stuff in `sycl/test/lit.cfg.py`.

**Describe the bug** https://github.com/triSYCL/sycl/blob/sycl/unified/next/sycl/doc/GettingStartedXilinxFPGA.md should be updated around **Running the test suite**

bug

I have tried the tool-chain on an Alveo U50 (with HBM memory :-) ) according to the documentation with: ```bash export XILINX_PLATFORM=xilinx_u50_gen3x16_xdma_201920_3 $SYCL_BIN_DIR/clang++ -std=c++20 -fsycl -fsycl-targets=fpga64_hls_hw_emu single_task_vector_add.cpp -o single_task_vector_add ```...

bug

I have the feeling that the change at the beginning of should not exist in https://github.com/triSYCL/sycl/compare/8677d5d562bb..6c7fac3aeb6#diff-4decc3bd7c76c920f705a179987a922f7d54b86636121a2cbb4441a7d6ace291