Ronan Keryell

Results 101 issues of Ronan Keryell

It would be nice to have Eigen-based project https://github.com/codeplaysoftware/SYCL-ML used to test triSYCL.

enhancement

As discussed first in https://github.com/triSYCL/triSYCL/pull/167 I realize that we had a `max_work_group_size` of 8, which is inconsistent with https://github.com/triSYCL/triSYCL/pull/167/files#diff-99cd0735cc7cfa70e53b6523b2d340ebR105 ``` TRISYCL_DEFINE_DEVICE_HOST_INFO_TEMPLATE(max_work_item_sizes, (cl::sycl::id{ 128, 128, 128 })) ``` It should be...

bug

Since Intel GPU are commodity and Beignet is both open-source and using recent Clang/LLVM, it should be possible to target it with the device compiler and SPIR-df.

enhancement

GitHub does not implement the ReST ``include:: ``directive https://github.com/github/markup/issues/172 which leads to replicate a lot of definition in SYCL documentation. :-( Perhaps using a preprocessor like https://github.com/github/markup/issues/1104 could be useful.

enhancement

The main issue is that `get_info()` can return different types according to `param` and in C++ it is not possible to have templated virtual functions, that could have been used...

bug
enhancement

Compilation error with g++ 11.2 ``` /var/tmp/rkeryell/SYCL/XRT/src/runtime_src/core/pcie/emulation/cpu_em/generic_pcie_hal2/shim.cxx: In member function ‘int xclcpuemhal2::CpuemShim::xclRegRW(bool, uint32_t, uint32_t, uint32_t*)’: /var/tmp/rkeryell/SYCL/XRT/src/runtime_src/core/pcie/emulation/cpu_em/generic_pcie_hal2/shim.cxx:983:14: error: ‘*(unsigned int*)((char*)&buff + offsetof(std::array,std::array::_M_elems[0]))’ may be used uninitialized in this function [-Werror=maybe-uninitialized] 983...

#### Problem solved by the commit Workaround dead-lock in hardware-emulation shutdown #### Bug / issue (if any) fixed, which PR introduced the bug, how it was discovered Just running some...

This is a followup to: https://github.com/Xilinx/XRT/pull/4418 While looking at it, it looks that there is a real issue in the code today even if actually it does not seem to...

While playing with the Intel SYCL implementation, @agozillon noticed that the file `cl_ext_xilinx.h` does not go to the standard OpenCL location while using the generated Debian XRT package. This makes...

In https://github.com/codeplaysoftware/syclacademy/blob/d92734607f51ef2ef9070bc7f84301ac7e189bc6/Lesson_Materials/Lecture_04_ND_Range_Kernel/index.html#L254 there are some mentions of constant memory which is no longer in SYCL 2020 but still in the OpenCL backend. This should be clarified.