Krzysztof Bieganski

Incorrect release of forced assignment

2

Verilator version: befb415f278af51fc3ecc3dda1dfe820de023bd1 Test case: ```systemverilog // verilator lint_off MULTIDRIVEN module t (clk); input clk; logic [31:0] lhs1, lhs2, rhs; logic cond = 0; always_comb lhs1 = rhs; assign lhs2...

Skip known bad vertices in power recovery

8

In power recovery, vertices that have already been tried and rejected can be tried again if they happen to be on another path we look at. Usually, the result is...

Types of interface members are not being translated from UHDM to Yosys' AST. An example of a struct in an interface: ```systemverilog interface foo; struct packed { logic [15:0] bar;...

drt: Push node index computation up

1

No functional change intended. This speeds up DRT by 3-8%, at least for `asap7` (varies depending on the design). Baseline is a recent commit from Oct 6. ## `asap7/aes` -...

Coverage breaks expressions with `this`

8

Some expressions that contain `this` are broken with `--coverage` enabled since 34ced254c0b1ebcf996dd922266faabd26da1869 (@toddstrader). For example, this: ```systemverilog class Foo; function logic test; return !this; endfunction endclass ``` Results in the...

This issue is at the root of the second problem reported in https://github.com/verilator/verilator/issues/3576. It's easiest to explain using an example. ```systemverilog module t(output logic clk_dly); logic clk = 0; always...

[xlscc] Expression cloning

4

This patch adds a Clang expression tree cloning utility to `xlscc`, as well as a unit test for it. It handles most C++ expressions, with one notable exception being lambdas...