Interface members missing types

[kbieganski]

Types of interface members are not being translated from UHDM to Yosys' AST. An example of a struct in an interface:

interface foo;
   struct packed {
       logic [15:0] bar;
   } baz = '1;
endinterface

module top(output int o);
   foo foo_();
   assign o = int'(foo_.baz.bar);
endmodule

Translates to:

    AST_MODULE <top.sv:7.0-7.0> [0x5602d30dcf50] str='\top' basic_prep
      AST_WIRE <top.sv:7.0-7.0> [0x5602d30e8460] str='\o' output signed basic_prep port=1 range=[31:0]
        AST_RANGE <top.sv:0.0-0.0> [0x5602d3ee29c0] basic_prep range=[31:0]
          AST_CONSTANT <top.sv:0.0-0.0> [0x5602d31e7750] bits='00000000000000000000000000011111'(32) signed basic_prep range=[31:0] int=31
          AST_CONSTANT <top.sv:0.0-0.0> [0x5602d3ed5500] bits='00000000000000000000000000000000'(32) signed basic_prep range=[31:0]
      AST_ASSIGN <top.sv:9.0-9.0> [0x5602d30dcc00] basic_prep
        AST_IDENTIFIER <top.sv:9.0-9.0> [0x5602d30e81a0 -> 0x5602d30e8460] str='\o' basic_prep
        AST_IDENTIFIER <top.sv:9.0-9.0> [0x5602d3153390 -> 0x5602d3ee3dd0] str='\foo_.baz.bar' basic_prep
      AST_CELL <top.sv:8.0-8.0> [0x5602d3ee1b00] str='\foo_' basic_prep
        AST_CELLTYPE <top.sv:0.0-0.0> [0x5602d3ee1c40] str='\foo' basic_prep
      AST_AUTOWIRE <top.sv:0.0-0.0> [0x5602d3ee3dd0] str='\foo_.baz.bar' basic_prep

    AST_INTERFACE <top.sv:0.0-0.0> [0x5602d3e6eba0] str='\foo'
      AST_WIRE <top.sv:4.0-4.0> [0x5602d3e61b80] str='\baz' logic range=[0:0]

Notice that baz in the interface definition is a simple [0:0] wire. A similar problem occurs with simpler types:

interface foo;
   parameter int W = 32;
   logic [W-1:0] bar = '1;
endinterface

module top(output int o);
   foo #(.W(16)) foo_();
   assign o = int'(foo_.bar);
endmodule

(same thing happens without the parameter, but it's important to consider when we work on it)

    AST_MODULE <top.sv:6.0-6.0> [0x5560c2d041a0] str='\top' basic_prep
      AST_WIRE <top.sv:6.0-6.0> [0x5560c3b32eb0] str='\o' output signed basic_prep port=1 range=[31:0]
        AST_RANGE <top.sv:0.0-0.0> [0x5560c3b340f0] basic_prep range=[31:0]
          AST_CONSTANT <top.sv:0.0-0.0> [0x5560c3b33130] bits='00000000000000000000000000011111'(32) signed basic_prep range=[31:0] int=31
          AST_CONSTANT <top.sv:0.0-0.0> [0x5560c3b32ff0] bits='00000000000000000000000000000000'(32) signed basic_prep range=[31:0]
      AST_ASSIGN <top.sv:8.0-8.0> [0x5560c3b0c760] basic_prep
        AST_IDENTIFIER <top.sv:8.0-8.0> [0x5560c3b32c70 -> 0x5560c3b32eb0] str='\o' basic_prep
        AST_IDENTIFIER <top.sv:8.0-8.0> [0x5560c3b0ad30 -> 0x5560c3b353d0] str='\foo_.bar' basic_prep
      AST_CELL <top.sv:7.0-7.0> [0x5560c3b333f0] str='\foo_' basic_prep
        AST_CELLTYPE <top.sv:0.0-0.0> [0x5560c3b33530] str='\foo' basic_prep
      AST_AUTOWIRE <top.sv:0.0-0.0> [0x5560c3b353d0] str='\foo_.bar' basic_prep

    AST_INTERFACE <top.sv:0.0-0.0> [0x5560c3ae1500] str='\foo' basic_prep
      AST_WIRE <top.sv:3.0-3.0> [0x5560c2cf8f50] str='\bar' logic basic_prep range=[0:0] 

I think it's likely this happens because the SV plugin takes the interface definition from uhdmallInterfaces, but it is incomplete. The full definition can be found under vpiInterface in the module that references the interface.

There might be further issues with getting complex types working with Yosys' internals, but producing a correct AST is the first step.