Krste Asanovic

Per issue #545, decided to omit Zvamo from initial standard vector extension. Need to define new encoding for post v1.0.

Choice of number of temp/arg/saved registers.

2

The number of temp/arg/saved registers and their location in/out of the 8 RVC registers needs quantitative support.

The current spec does not define a different hard-float EABI for system with f registers.

Big-endian behavior of whole register load/store

5

Big-endian implementations do not have the property that bytes in a vector register are held in the same order as in memory, and changing SEW will expose big-endianness. The whole-register...