Krste Asanovic

To make progress and clean up issue, will make change to add scliccfg then create new thread (issue #226) to discuss new proposal to use levels to separate modes.

This issue left here to track agreed change to add scliccfg.

Above commits addressed this issue.

The TG discussed this during fast-int meeting. Some comments: Code size is not a major concern with ISRs, but performance could be. Hardware stacking of CSRs might be a feature...

We revisited this topic again but decided to defer to broader discussion on providing hardware stacking of interrupt contexts (possibly post-1.0).

TG Meeting 2/1/2022. - attendees felt above was sufficient for arch tests

Unless every SEE always also has the hypervisor extension, the distinction still exists and is useful. There are effectively more privilege modes with the hypervisor extension, not fewer.

We can have an SBI or HBI without M-mode - a RISC-V M-mode is only one way to implement an SBI or an HBI. I think part of the confusion...

When taking a horizontal trap on a table fetch, the trap handler should not be trying to use MRET with the original inhv value, so we should simplify the logic...

Saying these values are reserved indicates that software should not use them. The hardware is not required to have a specific response. It is legal, but not required, to trap...