kai413629305

How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?

1

How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?Thank you!

About RocketCore.scala issue

8

Is there an analysis of RocketCore.scala in the rocket folder? Or is there more analysis of other scala files in the rocket folder?

firrtl-interpreter internal structure

2

What is the internal structure of firrtl-interpreter and what is the model? How to change the signal inside the model(poke or peek)? Can someone explain it? See the source code...