How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?

[kai413629305]

How to test the RISCV kernel developed with Verilog using rv32ui in riscv-tests?Thank you!

[WRansohoff]

I had the same question; I'm not sure if this is right, but I think you can just write a testbench which runs the operations from the assembly files under isa/rv32ui, and check the expected values:

https://github.com/riscv/riscv-tests/tree/master/isa/rv32ui

It looks like each instruction has its own assembly file (like add.S), and it seems like most of the 32-bit tests just #include the corresponding 64-bit test file:

https://github.com/riscv/riscv-tests/tree/master/isa/rv64ui