Jean-Paul Chaput

Yes I noticed this annoying management of underscore. I agree with the principle that we should modify as little as possible the original names. My only concern is about ``VHDL``....

I confirm, ``VHDL`` identifiers does not allow two consecutive underscore, and not trailing one either. So the translation should be moved at ``VHDL`` driver level. If we want to preserve...

Hello Myrtle, sorry, not yet. Lot of things to do for my lectures last week! Will try as soon as possible.

Hello Myrtle, I may have time to look into the problem in the next days. But my first question is the "specification". If we run straight through Coriolis from ``BLIF``...

> > If we run straight through Coriolis from BLIF to GDS, we should not have any naming problems. They should not be affected by . (dot) in names, it...

I may be wrong, but as far as I am concerned, the BLIF format is supported only because it's the output of Yosys. So the *reference* is what Yosys supports....

Thanks for pointig us out, Mithro, I was still on the dusty 1992 documentation. We will implement what's relevant to VLSI when I have a bit of spare time.

In case you didn't do it yet, in your output files display the ``ids`` of the various objects. The ``ids`` can be viewed as an *order* tag, or a *time...

If you have a *very small* design to test on, you can activate the *debug level* **0**, this will dump information on how the database itself is constructed. How the...

> That is worrying. Is the order consistent between runs? Might be worth putting together a determinism test. Comparing output on the different platforms would also make sense. > […](#)...