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high performance AES implementations optimized for cortex-m microcontrollers

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Hi, do you plan to add the an implementation using T-tables for the CM0 target? Thanks!

enhancement

Hey, this library looks awesome! Just curious if this can be used for AES-GCM ?

enhancement
1.0.0

ctx, input and output data need to be 4 byte aligned to not crash cm0 will crash even with unaligned `ldr` cm7 prefers 8 byte alignment for perf reasons

enhancement

otherwise no padding, will read and write past the in/out buffers

1.0.0

If true, then the last compressed processing instruction can leak secret data.

with risc-v implementations it's no longer cortexm

1.0.0

currently it takes space in flash, generation code should be smaller Somehow make sure that unused tables are not forced in, due to being generated rather than .data initialized enabled...

enhancement

qkv2 results contain additional instructions within measurement window. Should solve also call overhead bias.

enhancement
1.0.0

separated into corectness and perf and templated to reduce duplications

enhancement
1.0.0