jmason827

@GiuseppeDiGuglielmo yes I am also quite interested in this

@zarubaf hey Florian. we got the thing to work on VC707. not sure how I should go about sharing the changes we made -- what's the best way?

@Iripi97 yes, only Vivado tools. note that you'll need a license for Virtex 7 chips. right now I've just finished modifying all the code I could find in the repository...

@zarubaf copy that. the PR is in. really the only substantial changes we made were the addition of `mig_vc707.prj`, some changes to bus widths in `ariane_xilinx.sv`'s port list, and a...

@iripi97 @zarubaf > I had to [...] add another constraint for `trst_n` Whoops, this is totally my fault. Meant to change `trst` in the constraints file back to `trst_n`. >...

@Iripi97 this is the one I've been using (zipped because couldn't attach `*.bin` file): [bbl.zip](https://github.com/pulp-platform/ariane/files/3731069/bbl.zip)