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Support more FPGA boards
Do you plan to support other FPGA boards in addition to the current Genesys 2?
Is there any brother/sister board that you may suggest? Is there anything that we should really pay attention at?
There was actually an effort to see if we could use smaller boards like ARTY. Technically (afaik) it would fit, but there is not much more room left in the system after that, and for a development platform it is not ideal, this is why we moved to a larger board. Since we are mainly a research group, we do not have the bandwidth to support multiple boards. As Florian said, we are hoping that the community will provide (and maintain) additional FPGA targets.
Yes, we have looked at the arty board but it would indeed nearly use up all the space on there.
However, we recently discovered another board that might be a good fit for Ariane: the Avalanche board from Microsemi (https://www.microsemi.com/existing-parts/parts/139680).
- 300k LUTs
- 1gb Ethernet
- 512mb DDR3
- only 180$
Our current flow is based on Vivado so you would have to add a new flow with the Microsemi tools and their IPs which might be quite a bit of work. If you stay with Xilinx based boards the porting effort should be minimal.
I was considering two boards indeed for the port:
- Digilent Arty A7 whose chip is 1 order of magnitude smaller than the chip on the Genesys 2
- (or preferably for the reasons that you say) Xilinx Virtex VC707 whose chip is slightly bigger than the Genesys 2
If you think that the port to the VC707 is doable, I may consider a try with some help from you guys (just in case). What do you think?
VC707 should be easily possible. We actually had a system running on it in the past. Xilinx, as Moritz said, will allow you to re-use most of our flow. You will need to generate a different mig project file and adapt the constraints file. Definitely willing to help you with issues coming up!
Just wondering, why are you not using Genesys 2? Arty is cheaper I see that, but VC707 is quite an expensive board.
Xilinx development boards (like VC707) are really common in academia and usually we get them as a donation through University Programs (in US at least).
I am pretty sure the vc707-porting will be beneficial to many people.
@zarubaf or @GiuseppeDiGuglielmo Is there any new update with adding Ariane support for the VC707?
@zarubaf hey Florian. we got the thing to work on VC707. not sure how I should go about sharing the changes we made -- what's the best way?
@jmason827 Did you only use Vivado tools? If so I would be very interested in knowing how you did!
@Iripi97 yes, only Vivado tools. note that you'll need a license for Virtex 7 chips. right now I've just finished modifying all the code I could find in the repository to work for the VC707. as it stands, you should be able to make fpga in the root directory.
below is a list of files that were added/modified. the zip contains the new files themselves. replace the old files with the new and you should be able to make fpga for the VC707. let me know if you hit roadbumps.
NOTE: the ariane-for-vc707 BIN file is not in the zip; it wouldn't fit.
Hey @jmason827 that sounds awesome. So submitting a PR would be a first step, then we can review the code together and I can also give the flow a go on my side. What did you change? One of my concerns is that the flow we provide for the Genesys II is still working otherwise I am more than happy to accept your contributions.
Let me know how that works for you and sorry for the long silence, the thread kind of got overlooked. In case integration should be a problem lets start a new issue.
@zarubaf copy that. the PR is in.
really the only substantial changes we made were the addition of mig_vc707.prj, some changes to bus widths in ariane_xilinx.sv's port list, and a new .xdc.
we're just happy to potentially contribute -- we're really enjoying using Ariane over here!
I was able to make this work on VC707 with the bit file I got from http://www.princeton.edu/~cloud/openpiton/ and the bbl.bin that I generated using https://github.com/pulp-platform/ariane-sdk repository. I am enjoying using ariane as well so far. I tried to boot debian, but I couldn't. Is it possible to boot debian on vc707?
@jmason827 @zarubaf With the new changes to the repository the only addition I had to make on my end for it to work was to add another constraint for 'trst_n' which I set as one of the push buttons similarly to how 'trst' was defined as the center button. It does seem to get caught up when booting the Linux image build with the SDK repository. It is stuck on the line: "[ 26.165448 ] lowrisc-digilent-ethernet: Lowrisc ethernet platform (300000000-30007FFF) mapped to ffffffd004028000" Is there a reason for this? I am going to try the pre-built image to see if the same result occurs.
@zarubaf The booting gets stuck on the same line for the pre-built image. Should I move this discussion to the SDK issues section? And is there any way around this holdup?
@iripi97 @zarubaf
I had to [...] add another constraint for
trst_n
Whoops, this is totally my fault. Meant to change trst in the constraints file back to trst_n.
It does seem to get caught up when booting the Linux image build with the SDK repository.
I should note we did not hook up ethernet correctly. We've not figured out how, and we haven't needed it for our purposes yet.
In any case, I'm able to boot Linux using the build from the SDK repo:
I should probably also note, though, that running Linux seems to get screwy in two cases: 1. Tetris glitches out after a short time playing and 2. the cachetest executable terminates with an Illegal instruction error. This is the wrong thread to go into much detail, but I want to at least disclose these facts.
I'd be happy to accept this fixup as a PR.
- The
cachetestis currently ment to fail as we do not support delegating the performance counters to user mode. So access to the CSR will just trap with an illegal instruction. It was a bug beforev4.2that made these registers accessible to user mode. - We have seen similar things on the Tetris side. Are you using the UART which we provide? I'd suspect some problems with it. But it could also be the core of course.
@jmason827 Do you think you could post your bbl.bin file? I would like to check to see if it was maybe an issue on my end with generating the boot image which is causing it to hang up at the "lowrisc-digilent-ethernet: Lowrisc ethernet platform (30000000-30007FFF) mapped to …" line.
@Iripi97 this is the one I've been using (zipped because couldn't attach *.bin file):
@jmason827 Do you think you could do me one more favor please? Would it be possible for you to zip together your .bit , .mcs , and .prm files you used when you received the (full) output you posted earlier? We are trying to verify if it is a software or hardware issue on our end. Any response would be greatly appreciated!
I fixed the boot process on the VC707 by removing the ethernet node from the device tree (fpga/src/bootrom/ariane.dts). Regenerate the bootrom afterwards by running make all inside fpga/.
Regarding ethernet on the VC707. The PHY is connected to the FPGA using the SGMII interface. To use the ethernet core from Ariane, a SGMII to RGMII converter would be needed. I am not sure how much effort it would take to develop.
There is another option you could try. I was unfortunaly not able you get this option running on an VCU108 Board. The ethernet is split in two parts:
MAC (Media Access Controller) (AXI to GMII)
GMII to RGMII Bridge
Xilinx has a GMII to SGMII bridge IP Core https://www.xilinx.com/support/documentation/ip_documentation/gig_ethernet_pcs_pma/v16_1/pg047-gig-eth-pcs-pma.pdf
(Xilinx also offers a GMII to RGMII Bridge IP Core, currently only for the Zync family https://www.xilinx.com/support/documentation/ip_documentation/gmii_to_rgmii/v4_0/pg160-gmii-to-rgmii.pdf)
I tried to exchange the GMII to RGMII Bridge with the GMII to SGMII Bridge but was unsuccesfull so far.
@lukasauer I have tried modifying my 'ariane.dts' file to get the boot run to complete but it is still getting stuck on the "lowrisc-digilent-ethernet: Lowrisc ethernet platform …". Are you sure changing this is what fixed the boot for your VC707.
Make sure to also regenerate the bootrom after editing the device tree. You should see changes to fpga/src/bootrom/bootrom.h and fpga/src/bootrom/bootrom.sv afterwards.
@RaphaelKlink Good point, that should work. Please let us know if you get it working, that would be really helpful! :)
@lukasauer I'm slightly confused, whenever I execute 'make all' inside the 'fpga' directory it just begins the process of generating the bit-stream and MCS file with Vivado, it does not remake the bootrom. Is this changing of bootrom happening implicitly or should I be going to another directory to ensure this is happening?
You are right, I didn't remember the directory correctly. make all should be run from fpga/src/bootrom/. This will just rebuild the bootrom, you will have to rebuild the bit file afterwards. Also make sure that you have a RISC-V toolchain available.