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Intel staging area for llvm.org contribution. Home for Intel LLVM-based projects.
The AMDGPU backend supports sequential consistency ordering semantics for all atomics correctly and implements for all relevant architectures since GCN.
This reverts commit c02f915d42ac9bd1a3c4f2215d703b49b3a2173d since this Coverity issue is a false positive. `EventImpl` is always set when we pass it in the runtime, but the previous change suggests it might...
This issue captures code review discussions for https://github.com/intel/llvm/pull/2097. This LLVM pass basically "unwraps" LLVM vectors wrapped into `intel::gpu::simd` objects when they are used as function formal and actual parameters, plus...
C++ modules do not seem to currently work with intel/llvm when SYCL is used. I'm curious if this is likely to be added in the near future, or if there...
**Describe the bug** Running ```C++ #include #include int main(int, char**) { cl::sycl::default_selector device_selector; cl::sycl::queue queue(device_selector); std::cout
The usage is currently guarded by __SPIRV_USE_COOPERATIVE_MATRIX macro. It's a split from https://github.com/intel/llvm/pull/13316
Test file: https://github.com/huanghua1994/HPC_Playground/blob/master/SYCL/reduction_timing.cpp Compiler version: git commit 140c0d04b777d291956a88d59ee47f17c5f448b3 Compiler configuration: `buildbot/configure.py --cuda` Selected device: GTX 1070, CUDA version 11.0, driver version 455.38 Problem description: When using the DPC++ reduction library...
