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[SYCL][ABI Break] Remove "cl" namespace

9

As part of the change, also start using "inline namespace _V1" to allow possible future ABI-affecting changes.

aelovikov-intel

[SYCL] Fix debug info generation when integration footer is present

17

Two changes were made: Driver passes an absolute path to an original source file through -main-file-name if integration footer is enabled. Clang CodeGen uses the file specified through -main-file-name to...

zahiraam

This PR creates the `local_accessor` class by aliasing the accessor class with `target::local`. The motivation behind this is that `target::local` has been deprecated in favour of `local_accessor` in SYCL2020. The...

AidanBeltonS

[Driver][SYCL] Do not pull in late static device libs for AMD GPU

4

The addition of the new OpenMP offloading driver path, which unbundles archives later in the toolchain is interfering with the device linking behaviors involving AMD GPU targets for SYCL offload...

mdtoguchi

This in non-functional changes, will only make the document more readable. Signed-off by: Yuan, Alex

Alex-Shanyi-Yuan

1) remove unused c-tor of SYCLMemObjT: Details: include/CL/sycl/detail/sycl_mem_obj_t.hpp:79 2) remove unused getBufSizeForContext accepting cl_mem: Details: include/CL/sycl/detail/sycl_mem_obj_t.hpp:299

raaiq1

[SYCL][ABI-break] Remove host_half_impl::half

1

raaiq1

Removed from L0 plugin: 1) make_context(const std::vector &DeviceList, pi_native_handle NativeHandle) - Details: [source/backend/level_zero.cpp:65](https://github.com/intel/llvm/blob/784cfa13046e4874e1b8173e44231987bc7db2f8/sycl/source/backend/level_zero.cpp#L64) 2) make_queue(const context &Context, pi_native_handle NativeHandle) - Details: [source/backend/level_zero.cpp:93](https://github.com/intel/llvm/blob/784cfa13046e4874e1b8173e44231987bc7db2f8/sycl/source/backend/level_zero.cpp#L101)

raaiq1

[SYCL][ESIMD] Fix a compilation of mix of unnamed ESIMD and non ESIMD kernels

1

The purpose of this PR is to fix an issue that leads to runtime exception when unnamed ESIMD and non ESIMD kernels are present.

fineg74

[SYCL][CUDA] Enable CXX standard library funcs for CUDA backend

25

This PR allows CXX stdlib funcs to be used for NVPTX backend. See https://github.com/intel/llvm/discussions/6379 llvm-test-suite test: https://github.com/intel/llvm-test-suite/pull/1112 It also adds the compiler flag `"-fbundle-no-offload-arch"`, which allows device code bundles to...

hdelan