Yi-Chien Lin

Results 4 repositories owned by Yi-Chien Lin

A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-frequency) algorithm. The average SNR = 58.76.

RISC-V-CPU

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A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.

Systolic-Array-for-Smith-Waterman

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This work implements a dynamic programming algorithm for performing local sequence alignment. Through parallelism, it can run 136X times faster than a software running the same algorithm.

GCN-Inference-Acceleration-HLS

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An end-to-end GCN inference accelerator written in HLS