TimRudy

Hi Rog, thanks for your interest. I'll post what the 74244 will look like, and I need to check about the 74245 and try it - as it's really bidirectional...

Here is the 74244 code, .ice file attached: ``` // Octal tri-state buffer/driver module ttl_74244 #(parameter BLOCKS = 2, WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0, DELAY_OFF =...

OK, using an FPGA is a natural extension and in this specific case of doing tri-state tests, I think I'm safe to say it's basically necessary. Not sure if you...

Here is the 74245 code, .ice file attached: ``` // Octal tri-state bus transceiver module ttl_74245 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0, DELAY_OFF = 0) (...

Strange as it seems, that is the synthesizer's way of stating this:     "You did not put an `else` at the end of every `if` statement, even one simple `if`...

Similarly, thinking of improving the validations and errors: Why doesn't the `iverilog` layer that does the "Verify" (Ctrl R) do a simple check like that and complain about incomplete `if`s...