ice-chips-verilog

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Hello there,

It'll be good if we have the 74244 and 74245 too in the list. :)

Thank you! Tri-state is a special case but these are on my TO-DO list

Do you think it likely that you will add these chips? They would be mighty handy. Thanks for reading!

Hi Rog, thanks for your interest. I'll post what the 74244 will look like, and I need to check about the 74245 and try it - as it's really bidirectional through the inout ports. I'll do some testing on the 74245, meanwhile you can test and try the 74244!

Here is the 74244 code, .ice file attached:

// Octal tri-state buffer/driver

module ttl_74244 #(parameter BLOCKS = 2, WIDTH = 4, DELAY_RISE = 0, DELAY_FALL = 0, DELAY_OFF = 0)
(
  input [BLOCKS-1:0] OE_bar,
  input [BLOCKS*WIDTH-1:0] A_2D,
  inout [BLOCKS*WIDTH-1:0] Y_2D
);

//------------------------------------------------//
wire [WIDTH-1:0] A [0:BLOCKS-1];
reg [WIDTH-1:0] computed [0:BLOCKS-1];
integer i;

always @(*)
begin
  for (i = 0; i < BLOCKS; i++)
  begin
    if (!OE_bar[i])
      computed[i] = A[i];
    else
      computed[i] = {WIDTH{1'bz}};
  end
end
//------------------------------------------------//

`ASSIGN_UNPACK_ARRAY(BLOCKS, WIDTH, A, A_2D)
assign #(DELAY_RISE, DELAY_FALL, DELAY_OFF) Y_2D = `PACK_ARRAY(BLOCKS, WIDTH, computed)

endmodule

Comments:

• I tested in Icestudio a bit, but I'm not sure yet how complete the functionality is
• Examples of errors that it's easy to create: 1) wire the inout port (1Y1) to a gate instead of an LED output (LED output works fine) - 2) wire the inout port to two things, like two LEDs
• So I'd love to hear of your testing, you can find my e-mail on Wiki page
• I tested the bidirectional 74245, and I think Icestudio may need capability update to wire to inout ports on the left/input side, let me check more

74244_Buffer_3State.zip

Thank you for the response, and your efforts.

I have been looking for a hands on type simulator- something with emulated push buttons and leds.

I am very new at this... suggestions are welcome...

I have an idea for a reasonable test, a system of octal flip-flop registers that share a common bus, with control lines to to determine which transceivers are active, so as.to load data into a particular register, copy.data between them, and output back to the bus. I can build this in icestudio, but would prefer an interactive test.

I don't want to complicate things by using a real fpga just yet if I can avoid it, but I realise that might not be easy. Verilator, so I read, doesn't like Tri-state, and iverilog seems somewhat less interactive.

This will be the first test bench I have ever tried to write...

Thanks again!

OK, using an FPGA is a natural extension and in this specific case of doing tri-state tests, I think I'm safe to say it's basically necessary. Not sure if you have one. Are you getting familiar with creating a test bench and an .ice circuit that builds for FPGA? Use "View -> Command output" and you see iverilog running for "Verify", you see yosys running for "Build". Simulating the Z is pretty normal for iverilog and it doesn't tell us much. Getting the Z buses written using yosys, onto FPGA, and seeing that they physically follow the rules is my current goal (and much neglected - I'm actually still not getting to it). The low or high voltage or "no signal" needs to either go to an LED or more likely to a GPIO pin to be seen and measured outside the FPGA. An LED can't indicate the difference between a "no signal" and a low voltage - unfortunately. But see if you can prove and disprove your logic functionality using a circuit with a bus as you describe.

-> Following the rules for tri-state means the bus gives a low or high voltage based on which input, which state. I need to check that with a multimeter. -> Following the desired, advanced rules for tri-state, supported by Icestudio, goes further: It allows the bus to go down into modules using "inout", and back up to top level, and we get the same successful physical results.

Just a note: This didn't get mentioned explicitly: This discussion assumes and requires the latest Icestudio Nightly version 0.11.2w... after approx Oct 31, 2023.

Here is the 74245 code, .ice file attached:

// Octal tri-state bus transceiver

module ttl_74245 #(parameter WIDTH = 8, DELAY_RISE = 0, DELAY_FALL = 0, DELAY_OFF = 0)
(
  input Dir,
  input OE_bar,
  inout [WIDTH-1:0] A,
  inout [WIDTH-1:0] B
);

//------------------------------------------------//
reg [WIDTH-1:0] A_computed;
reg [WIDTH-1:0] B_computed;

always @(*)
begin
  if (!OE_bar)
  begin
    if (Dir)
    begin
      A_computed = {WIDTH{1'bz}};
      B_computed = A;
    end
    else
    begin
      A_computed = B;
      B_computed = {WIDTH{1'bz}};
    end
  end
  else
  begin
    A_computed = {WIDTH{1'bz}};
    B_computed = {WIDTH{1'bz}};
  end
end
//------------------------------------------------//

assign #(DELAY_RISE, DELAY_FALL, DELAY_OFF) A = A_computed;
assign #(DELAY_RISE, DELAY_FALL, DELAY_OFF) B = B_computed;

endmodule

Comments:

• I can't see it will be any different from this finally
• Testing not done

74245_Bus_Transceiver_3State.zip