TimRudy

The adder16.ice is at https://github.com/TimRudy/ice-chips-verilog/tree/Arithmetic/source-arithmetic, for you to play with

OK, as next step I put up 2 different comparators comparator16-unsigned.ice, comparator16-signed.ice Run test benches with: iverilog -g2012 -ocomparator-tb.vvp ..\includes\tbhelper.v comparator-signed-tb.v comparator-signed.v For me test benches are what we need;...

This is a good feature that could be integrated in Icestudio. Alex already did most of the leg work: - Auto-populate the module ports dialog by parsing a Verilog code...

Hi Meind, I had the same issue (FPGAwars issue #234), and tried all kinds of software/driver and Zadig/install attempts, but it isn't a software issue, it is an issue where...

Different issue, getting APIO working. The Windows issue was  or 

I guess this refers to the Node.js source code of Icestudio? Anyone who has an improvement for Icestudio is welcome to create a PR, and that's how improvements will happen....

I think you're on your own to use that skeleton and get the test bench doing what you want (from your learning). You'll find examples. Mine use a macro (`"TBASSERT"`)...

I don't understand this (English translation). It seems that `xx` can be connected to `yy` with a wire (2 DIFFERENT labels). That is accepted. It is shown visually. But it...

Hi, these ideas are some gems and they're hidden here, not related to the issue title :-) Shall we create official issues for wish list? More issues for wishlist, transcribed...

From comment by Joaquim @jojo535275: 12. One day it will be nice to have a warning to the user somewhere when we load a design which contains old blocks versions...