Ricky Su

Hi @belanasaikiran , I find this error message is pointing to Vitis-AI layer. May I know which tutorial are you working on? We need to do further investigation. Thanks.

Hi @randyh62 , could you help with this question? Hi @m-kru , it's recommended to ask this generic question in the forums: http://forums.xilinx.com/

Could you try `chmod -R 777` for your working directory?

Hi @nikhil2k10 , I assume you need to create a Vitis platform for your development kit. Some issue may occur during your customization. Hanging at cl:finish();/q.finish() may relate to the...

Hi @nikhil2k10 , line 280 `interrupt-parent = ;` is commented out. It's needed for zyxclmm_drm. You need to find out the interrupt controller node name in your design (check other...

Hi @nikhil2k10 , this line tells ZOCL driver which interrupt it should use. The ZCU104 platform example writes this node because in the hardware XSA, the interrupt controller is called...

Hi @SURUTHI1605 , I think this lenet issue has been solved. Please confirm.

In 2022.2 branch, the makefile path is now https://github.com/Xilinx/Vitis-Tutorials/blob/2022.2/AI_Engine_Development/Design_Tutorials/01-aie_lenet_tutorial/Makefile . Please fix in the latest branch. Please document the environment variables need to be set before running the makefile, e.g....

Running FSBL in verbose mode is OK for healthy boards. But since FSBL runs ps7_init/psu_init() in C style, if something goes wrong in ps7_init/psu_init(), it's hard to say it's a...

Closing this issue due to no response from reporter. Please reopen if you encounter the same issue or can provide more info.