Checking timing violation path

[m-kru]

I have received negative slack for my kernel. Is there any way to identify logic path causing the timing violation from the Vitis HLS GUI? I feel like I have gone though all reports, clicked all possible icons, but still no info on operations causing the timing violation.

[imrickysu]

Hi @randyh62 , could you help with this question?

Hi @m-kru , it's recommended to ask this generic question in the forums: http://forums.xilinx.com/

[m-kru]

@imrickysu The one that Xilinx wipes out once every few years, so that people cannot see how many bugs are in the Xilinx software?

[randyh62]

Which version are you working with?

[m-kru]

2021.2

[randyh62]

You can run Vivado Synthesis and Implementation to generate timing reports from Vitis HLS. You can do this from the Implementation menu in the Flow Navigator, or by using the config_export command and then running export_design in a Tcl script.

I am attaching some screenshots from the 2021.2 release for your review.