Ricky Su

Hi @dongzhang2021 , could you attach the logs in Vivado console? I wish to check the Tcl command for export and the full error message. Thanks.

Hi @IvoBrandao , Dongzhang created another thread in https://github.com/Xilinx/Vitis-Tutorials/issues/144 but didn't add more reply. May I know which OS you're running? Is it Windows or Linux? Is there any modifications...

Hi @randyh62 , could you look at this Getting started guide feedback? Thanks.

We don't have pre-built ZCU106 base platform, but ZCU106 is very similar to ZCU104. You can follow https://github.com/Xilinx/Vitis-Tutorials/tree/2022.1/Vitis_Platform_Creation/Design_Tutorials/02-Edge-AI-ZCU104 and use Vivado ZCU106 board file. You can also use the ZCU104...

The `AIE_METADATA err: -22` can be safely ignored. It's an XRT code issue. The wrong result can be caused by many reasons. Checking with Vitis-AI experts.

The v++ configuration settings is set by https://github.com/Xilinx/Vitis-AI/blob/v1.3/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_gui and this file is associated to the application project by https://github.com/Xilinx/Vitis-AI/blob/v1.3/dsa/DPU-TRD/description.json In `description.json`, the `"ldclflags" : "--config PROJECT/src/prj/Vitis/config_file/prj_config_gui"` is set under `platform_properties`->...

Hi @Ali-Flt , I reran the VAI test for 2020.2. It worked well on my side. Could you try to create the Vitis-AI application with the platform generated by the...

Hi @LoeWHJ , could you share more details in your question? Do you mean this folder? https://github.com/Xilinx/Embedded-Design-Tutorials/tree/master/docs/Introduction/ZynqMPSoC-EDT/ref_files Embedded Design Tutorials is a github repo outside of Vitis-Tutorials.

@Rampagee Could you share more info about the case with 30,000MB/s PCIe throughput? Hi @anonymous1782 , for general Vitis questions, we recommended you post in http://forums.xilinx.com/. AMD/Xilinx Tech Support team...

Hi @Rampagee , could you add license expectation to the tutorial? Thanks.