hust-gaoyujing

where can i find the simulation logs?

2

After finishing the simulation(run-verilator.sh) ,where can i find the simulation logs that record the results of simulation and the counters of SOC? Or whether it have simulation logs?

Is it correct that it generate so many VTestHarness__*.o/cpp when i use `./scripts/build-verilator.sh --debug`

4

**Problem:** when i use the command_line `./scripts/build-verilator.sh --debug` (for a simulator that can generate waveforms), it generate so many files(VTestHarness__115.o VTestHarness__115.cpp) in the folder(sims/verilator/generated-src/chipyard.TestHarness.CustomGemminiSoCConfig/chipyard.TestHarness.CustomGemminiSoCConfig.debug), and it seems to continue. So...

Is there a document depicting `config_norm` in branch "mlsys-tutorial-2022"?

4

I am so interested in the new thing "norm" when i read the codes in branch "mlsys-tutorial-2022", but i can't find a document for it to understand its function and...

How to generate the waveform of some modules but not all of the system?

3

When i used the command `./scripts/build-verilator.sh --debug` to simulate and generate some waveforms, i found the waveform files (.vcd) is so big (maybe more than 100G) that it's so hard...

"bad syscall #98!" error in running inference

5

**Describe the bug** I just follow the command lines from Gemmini Tutorial IISWC 2021. 1.It work fine that run `./build.sh --parallel --enable_training --config=Debug --cmake_extra_defines onnxruntime_USE_SYSTOLIC=ON onnxruntime_SYSTOLIC_INT8=ON onnxruntime_SYSTOLIC_FP32=OFF` in `/gemmini/software/onnxruntime-riscv/` 2.`./build.sh...