pito_riscv
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hossein1387
A Barrel design of RV32I
Pito's decoder module is a lookup table. For ASIC this implementation is very expensive. We need a better decoder unit for ASIC flow.
Pito pipeline contains a lot of unnecessary code and should be cleaned.
Currently PITO pipeline executes any instruction that is fed into the pipeline. Pito verification monitor prevents simulation to run if unsupported/ Unknown instruction is fetched for execution. However, we should...
- [ ] Cleanup code in `rv32_core.sv`. Many signals are not being used. - [ ] Comments in most files are outdated. - [ ] Change module names from `rv32_*`...
After adding the new APB interface in CSR module, the long comb blocks from decoder to APB transaction is making pito not meet timing (200MHz).
In some test scenarios, the predictor module outputs FAIL without it actually being a failure. Early investigation shows that these are mostly related to improperly initializing the Data RAM.