Digital

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Add Program Clock

3

This is not a bug report, but it would be nice if one could implement a program clock. What I mean is, if you have one clock in a simulation,...

AsparaGus116


radiantgurl

Changing the name

44

I'm sure it sounds a bit too extreme, but please give it a short consideration. As a guy who really loves your SW, I'd like to put my files on...

vladtyum

adding a pause button

3

Add a pause button to pause/resume the running clocks.

hneemann

Digital.exe requires Java 8

21

After downloading `v0.29` and executing `Digital.exe` I get prompted with a message that tells me that JRE 8.0 is required. Although your README states: > A [Java Runtime Environment](https://www.java.com/) (at...

Likqez

> This is not a bug report. Not sure whether you are aware or not, but I just came across a similar project (software) used to design circuits. It's called...

hinell

Document test error

3

I got test error when running `mvn install` with the most recent source code (commit hash is 1951d7aee84ae756e42f72c05faae7d19ad681ac). ``` [ERROR] Failures: [ERROR] DocuTest.testDocu:337->startFOP:287 [INFO] [ERROR] Tests run: 815, Failures: 1,...

VitalyAnkh

Currently there is only a single DP-RAM component and due to it's asynchronous reading Quartus is unable to make use of an FPGA's internal BlockRAM. which is a shame as...

ProxyPlayerHD

Request: VCD output of signal waveforms for use with gtkwave

3

It would be awesome if Digital had a mode where the signals in the waveform viewer could be logged to a VCD file, especially if it supports dumping single step...

rj45

Verilog code with $readmemh

1

Hi Neemann! In order to fill memory contents I code in Verilog file: initial $readmemh("RV32I_memory.txt",Memory); I can with success the file in Digital, and export also the design file to...

j054n