Synchronous Dual Port RAM for FPGAs?

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Currently there is only a single DP-RAM component and due to it's asynchronous reading Quartus is unable to make use of an FPGA's internal BlockRAM. which is a shame as most BlockRAM is already Dual Port.

so would it be possible to get a second DP-RAM component that only updates the 1D and 2D outputs on the rising egde of the Clock?