Verilog code with $readmemh

[j054n]

Hi Neemann! In order to fill memory contents I code in Verilog file: initial $readmemh("RV32I_memory.txt",Memory); I can with success the file in Digital, and export also the design file to Verilog again, but I can simulate correctly into Digital, It seems not execute the sentence. Which is the reason for it? Thanks in advance and best regards, Josan M

[hneemann]

In the simulator, ram can only be initialized if it is marked as program memory. In general, ram can not be initialized. And also in Verilog or VHDL this is not a good idea, because if ram is initialized here, no blockram can be used for synthesis as far as I know.