Hesham Almatary
Hesham Almatary
Right now processor_t::reset is being called when sim_t is created. That's before spike_main is able to register an extension. This doesn't reset the extension (ext->reset()) as ext is still null...
Support for building and running seL4 on the new Arm's Morello which has CHERI extension. However, this PR only supports AArch64 without CHERI yet. This servers as a baseline architecture...
This commit adds a new Arm's Morello board platform to seL4 also known as morello-soc. It only supports AArch64 mode without CHERI support and could be built with either GCC...
This commit adds a new Arm's Morello FVP platform to seL4. It only support AArch64 mode without CHERI support and could be built with either GCC or LLVM/lld. Morello FVP...
This issue is a tracker for adding baseline Morello support including a new CPU and platforms. It is just like any other AArch64 CPU/platform **_without_** any CHERI support. Currently, I...
Currently the non-hyp AArch64 port only supports up to 47-bit Physical Address (PA) space due to how virtual memory mapping is implemented and a bitfield generator limitation with device untyped....
The existing `qemu-arm-virt` works with GICv2. GICv3 hasn't been tested with seL4 on QEMU. This discussion was raised in this PR #1157. Trying to run seL4 on QEMU/GICv3 halts on...
This is a Morello hardware platform also known as morello-sdp board. This is mostly derived from the existing FVP platform; the main changes are the UART and timer addresses and...
This is mostly derived from the existing FVP platform; the main changes are the UART and timer addresses and IRQ IDs. Just two drivers are supported, PL011 for the console...